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1 of 27 GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 GS2975A hd-linx? iii multi-rate sd i automatic reclocker with dual differential outputs www.gennum.com features ? smpte 424m, 292m, and 259m-c compliant ? supports data rates of 270, 1483.5, 1485, 2967, 2970mb/s ? supports dvb-asi at 270mb/s ? pb-free and rohs compliant ? auto and manual modes for rate selection ? standards indication in auto mode ? 4:1 input multiplexer patented technology ? choice of dual reclocked data outputs or one data output and one recovered clock output ? footprint and drop-in compatible with existing gs2975 designs ? loss of signal (los) output ?lock detect output ? on-chip input and output termination ? differential 50 inputs and outputs ? mute, bypass and autobypass functions ? sd/hd indication output to control gs2978 dual slew-rate cable driver ? single 3.3v power supply ? operating temperature range: 0c to 70c applications ? smpte 424m, smpte 292m an d smpte 259m-c serial digital interfaces description the GS2975A is a multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the GS2975A serial digital reclocker will recover the embedded clock signal and re-time the data from a smpte 424m, smpte 292m, or smpte 259m-c compliant digital video signal. the GS2975A removes the hi gh frequency jitter components from the bit-serial stream. input termination is on-chip for seamless matching to 50 transmission lines. the GS2975A can operat e in either auto or manual rate selection mode. in auto mode the device will automatically detect and lock onto incoming smpte sdi data signals at any supported rate. for single rate data systems, the GS2975A can be configured to operate in manual mode. in both modes, the device requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. in systems which require passing of non-smpte data rates, the GS2975A can be configured to either auto matically or manually enter a bypass mode in order to pass the signal without reclocking. the GS2975A offers a choice of dual reclocked data outputs or one data output and one recovered clock output. the device is footprint and drop-in compatible with existing gs2975 designs, with no addi tional application changes required. the GS2975A is pb-free, and th e encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous sub-components are rohs compliant.
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 2 of 27 functional block diagram GS2975A functional block diagram revision history xtal+ xtal- xtal out- xtal out+ ddi_sel[1:0] ddi 1 ddi 2 ddi 3 ddi 0 lf+ lf- kbb ddo_mute ddo 0 autobypass bypass locked auto/man ss[2:0] xtal osc buffer data buffer vco bypass logic divider phase frequency detector divider control logic charge pump m u x d a t a m u x m u x re-timer phase detector sd/hd rco_mute rco/ddo1 clock buffer los m u x data/clock version ecr pcn date changes and/or modifications 4 151358 ? april 2009 added 2.5k reel option to section 6.6 ordering information . c hanged the maximum input swing value from 800mv to 1100mv in table 2-2: a c electrical c haracteristics . 3 150068 ? june 2008 removed references to g nd_drv in s ection 1.1 gs 2975a pin assignment and table 1-1: pin descriptions . 2 147068 ? august 2007 typo: functional block diagram on page 2 . 1 146316 ? july 2007 typo: pin 64 in table 1-1 & ta c figure 5-1 on page 22 , pins 38/40 & 44/46 in table 1-1 . 0 143947 43428 february 2007 c onverting to data s heet. removed ?proprietary and c onfidential? footer. updated a c electrical c haracteristics table. added junction - board thermal resistance parameter to 6.3 packaging data . added section 6.4 marking diagram .
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 3 of 27 contents features....................................................................................................................... ..........................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagram ..................................... .................................................................. .......................2 revision history ............................................................................................................... ..................................2 1. pin out..................................................................................................................... ..........................................4 1.1 GS2975A pin assignment .................................................................................................... ..........4 1.2 GS2975A pin descriptions .................................................................................................. ...........5 2. electrical characteristics .................................................................................................. ..........................8 2.1 absolute maximum ratings .................................................................................................. ........8 2.2 dc electrical characteristics ...... ....................................................................................... ...........8 2.3 ac electrical characterist ics ............................................................................................. ........ 10 3. input/output circuits ....................................................................................................... ........................ 13 4. detailed description........................................................................................................ .......................... 16 4.1 slew rate phase lock loop (s-pll) ......................................................................................... 16 4.2 vco ....................................................................................................................... ............................. 17 4.3 charge pump ............................................................................................................... .................... 17 4.4 frequency acquisition loop ? the phase-frequency detector .................................. 18 4.5 phase acquisition loop ? the phase detector ................................................................... 18 4.6 4:1 input mux ............................................................................................................. ..................... 19 4.7 automatic and manual data rate selection ......................................................................... 19 4.8 bypass mode ............................................................................................................... .................... 20 4.9 dvb-asi operation ......................................................................................................... .............. 20 4.10 lock and los ............................................................................................................. ................... 20 4.11 output drivers and output mute .......................................................................................... 2 1 5. typical application circuit ......... ........................................................................................ .................... 22 6. package & ordering information .............................................................................................. ............ 23 6.1 package dimensions ........................................................................................................ ............. 23 6.2 recommended pcb footprint .. ........... ........... ........... ........... ........... ........... ........... ........... ....... .. 24 6.3 packaging data ............................................................................................................ ................... 25 6.4 marking diagram ........................................................................................................... ................ 25 6.5 solder reflow profiles .................................................................................................... .............. 26 6.6 ordering information ...................................................................................................... ............. 26
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 4 of 27 1. pin out 1.1 GS2975A pin assignment figure 1-1: 64-pin qfn ddi0 nc 6 4-pin qfn (top view) 1 ddi0_vtt ddi0 gnd ddi1 ddi1_vtt ddi1 gnd ddi2 ddi2_vtt ddi2 gnd ddi3 ddi3_vtt ddi3 gnd lf+ nc nc nc nc nc xtal- xtal+ xtal_out- xtal_out+ gnd vee_ddo vcc_ddo rsv gnd vee_rco vcc_rco rco/ddo1 rsv rco/ddo1 kbb ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco locked ss0 ss1 ss2 los vcc_dig vee_dig gnd vcc_cp vee_cp nc ddo0 ddo0 1 6 17 32 33 48 49 6 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 2 6 27 28 29 30 31 22 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 50 51 52 53 54 55 5 6 57 58 59 6 0 6 1 6 2 6 3 lf- groun d pa d ( b ottom of pa c ka g e) nc auto/man ? ? ? ? ddo_mute sd/hd GS2975A rco_mute data/clock
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 5 of 27 1.2 GS2975A pin descriptions table 1-1: pin descriptions pin number name ty p e description 1, 3 ddi0, ddi0 input s erial digital differential input 0. 2 ddi0_vtt passive c enter tap of two 50 on-chip termination resistors between ddi0 and ddi0 . 4, 8, 12,16, 32, 43, 49 g nd passive recommended connect to g nd. 5, 7 ddi1,ddi1 input s erial digital differential input 1. 6 ddi1_vtt passive c enter tap of two 50 on-chip termination resistors between ddi1 and ddi1 . 9, 11 ddi2, ddi2 input s erial digital differential input 2. 10 ddi2_vtt passive c enter tap of two 50 on-chip termination resistors between ddi2 and ddi2 . 13, 15 ddi3, ddi3 input s erial digital differential input 3. 14 ddi3_vtt passive c enter tap of two 50 on-chip termination resistors between ddi3 and ddi3 . 17, 18 ddi_ s el[1:0] logic input s erial digital input select. 19 bypa ss logic input bypass the reclocker stage. when bypa ss is hi g h, it overwrites the autobypa ss setting. 20 autobypa ss logic input automatically bypasses the recl ocker stage when the pll is not locked this pin is ignored when bypa ss is hi g h. 21 auto/man logic input auto/manual select. when set hi g h, the standard is automatically detected from the input data rate. when set low, the user must program the input standard using the ss [2:0] pins. 22 v cc _v c o power most positive power supply connection for the internal v c o section. c onnect to 3.3v. 23 vee_v c o power most negative power supply connection for the internal v c o section. c onnect to g nd. ddi_ s el1 ddi_ s el0 input s ele c ted 0 0 ddi0 0 1 ddi1 1 0 ddi2 1 1 ddi3
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 6 of 27 24, 25, 26 ss [0:2] bi-directional when auto/man is hi g h, ss [0:2] are outputs, displa ying the data rate to which the pll has locked. when auto/man is low, ss [0:2] are inputs, forcing the pll to lock only to a selected data rate . 27 n c no c onnect not connected internally. 28 lo c ked output lock detect. this pin is set hi g h by the device when the pll is locked. 29 lo s output loss of s ignal. s et hi g h when there are no transitions on the active ddi[3:0] input. 30 v cc _di g power most positive power supply conn ection for the internal glue logic. c onnect to 3.3v. 31 vee_di g power most negative power supply connection for th e internal glue logic. c onnect to g nd. 33 s d/hd output this signal will be set low by the device when the reclocker has locked to 2.97 g b/s (2.967 g b/s) or 1.485 g b/s (1.4835 g b/s), or when a non- s mpte standard is applied (i.e. the device is not locked). it will be set hi g h when the reclocker has locked to 270mbps. 34 kbb analog input c ontrols the loop bandwidth of the pll. 35 r c o_mute power s erial clock or secondary data output mute. assert low for reduced power consumption, see 2.2 d c electrical c haracteristics . when r c o_mute = low, the r c o/ddo1 output is powered down. when r c o_mute = hi g h, the r c o/ddo1 output is active. note: this is not a logic input pin. table 1-1: pin descriptions (continued) pin number name ty p e description ss 2 ss 1 ss 0 data rate s ele c ted/for c ed (mb/s) 010 270 1 0 1 1483.5/1485 1 1 0 2967/2970
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 7 of 27 36 ddo_mute logic input mutes the ddo0 and/or r c o/ddo1 outputs. 37 data/ c lo c k logic input data/ c lock select. when set hi g h, the r c o/ddo1 pin will output a copy of the serial digital output (ddo0). when set low, the r c o/ddo1 pin will output a re-timed clock (r c o). 38, 40 r c o/ddo1, r c o/ddo1 output s erial clock or secondary data output. when r c o_mute is connected to v cc , the serial digital differential clock or secondary data output will be presented. 39, 45 r s v reserved do not connect. 41 v cc _r c o power most positive power su pply connection for the r c o/ddo1 and r c o/ddo1 output driver. c onnect to 3.3v. 42 vee_r c o power most negative power su pply connection for the r c o/ddo1 and r c o/ddo1 output driver. c onnect to g nd. 44, 46 ddo0 , ddo0 output differential s erial digital outputs. 47 v cc _ddo power most positive power supp ly connection for the ddo0/ddo0 output driver. c onnect to 3.3v. 48 vee_ddo power most negative power su pply connection for the ddo0/ddo0 output driver. c onnect to g nd. 50, 51 xtal_out+, xtal_out- output differential outputs of the referenc e oscillator used for monitoring or test purposes. 52, 53 xtal+, xtal- input reference crystal input. c onnect to the g o1535 as shown in the typical application c ircuit on page 22 . 54 - 59 n c no c onnect not connected internally. 60 vee_ c p power most negative power supply conn ection for the internal charge pump. c onnect to g nd. table 1-1: pin descriptions (continued) pin number name ty p e description ddo_mute r c o_mute data/ c lo c k ddo0 r c o/ddo1 11 0data c lo c k 1 1 1 data data 01 0mute c lo c k 0 1 1 mute mute 10 xdatapower down 00 xmutepower down note: mute = outputs latched at previous data bit. power down = outputs pulled to v cc through 50 resistor.
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 8 of 27 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics 61 v cc _ c p power most positive power supply connecti on for the internal charge pump. c onnect to 3.3v. 62, 63 lf+, lf- passive loop filter capacitor connection. c onnect as shown in the typical application c ircuit on page 22 . 64 n c no c onnect not connected internally. recommended connect to g nd. ? c enter pad ? g round pad on bottom of package. s older to main ground plane following recommendations under recommended p c b footprint on page 24 table 1-1: pin descriptions (continued) pin number name ty p e description parameter value s upply voltage range -0.5v to +3.6 v d c input voltage range v ee - 0.5v to v cc + 0.5v operating temperature range -20 c to 85 c s torage temperature range -50 c < t s < 125 c input e s d voltage 4kv hbm, 100v mm s older reflow temperature 260 c note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the a c /d c electrical c haracteristic sections is not implied. table 2-1: dc electrical characteristics v cc = 3.3v 5%, t a = 0 c to 70 c , unless otherwise shown. typical values: v cc = 3.3v and t a =25 c parameter symbol conditions min ty p max units s upply voltage v cc operating range 3.135 3.3 3.465 v s upply c urrent i cc r c o/dd01 enabled ? 142 170 ma i cc r c o/ddo1 disabled ? 123 152 ma
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 9 of 27 power c onsumption ? r c o/dd01 enabled ? 468 590 mw ?r c o/dd01 disabled ? 404 528 mw logic inputs ddi_ s el[1:0], bypa ss , autobypa ss , auto/man , a s i/177 , ddo_mute v ih high 2.0 ? ? v v il low ? ? 0.8 v logic outputs s d/hd, lo c ked, lo s v oh i oh = -2ma 2.4 ? ? v v ol i ol = 2ma ? ? 0.4 v bi-directional pins (manual mode) ss [2:0], auto/man = 0 v ih high 2.0 ? ? v v il low ? ? 0.8 v bi-directional pins (auto mode) ss [2:0], auto/man = 1 v oh i oh = -2ma 2.4 ? ? v v ol i ol = 2ma ? ? 0.4 v xtal_out+, xtal_out- v oh high ? v cc - 0.075 ? v v ol low ? v cc - 0.300 ? v r c o_mute ? i = -1.5ma v cc - 0.165 v cc v cc + 0.165 v s erial input voltage ? c ommon mode 1.65 + (v s id /2) ?v cc - (v s id /2) v s erial output voltage ddo0/ddo0 , r c o/ddo1 / r c o/ddo1 ? c ommon mode ? v cc - (v od /2) ? v table 2-1: dc electrical characteristics (continued) v cc = 3.3v 5%, t a = 0 c to 70 c , unless otherwise shown. typical values: v cc = 3.3v and t a =25 c parameter symbol conditions min ty p max units
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 10 of 27 2.3 ac electrical characteristics table 2-2: ac electrical characteristics v cc = 3.3v 5%, t a = 0 c to 70 c , unless otherwise shown. typical values: v cc = 3.3v and t a =25 c parameter symbol conditions min ty p max units notes s erial input data rate ? ? 270 ? 2970 mb/s ? s erial input jitter tolerance ? worst case modulation (e.g. square wave modulation) 270, 1485, 2970 mb/s 0.8 ? ? ui ? pll lock time - asynchronous t alo c k ??1.510ms? pll lock time - s ynchronous t s lo c k kbb = float, c lf=47nf s d/hd = 0 ?0.5 4 s? kbb = float, c lf=47nf s d/hd = 1 ?520 s? s erial output rise/fall time s do0 and r c o/ddo1 (20% - 80%) t r s do ,t rr c o 50 load (on chip) ? 110 ? ps ? t f s do ,t fr c o 50 load (on chip) ? 110 ? ps ? s erial digital input s ignal s wing v s id differential with internal 100 input termination s ee figure 2-1 100 ? 1100 mv p-p ? s erial digital output s ignal s wing ddo0 and r c o/ddo1 v od 100 load differential s ee figure 300 450 600 mv p-p ? ddo0 to ddo1 skew dd skew ? ? 156 ? ps 1 ddo0 to r c o skew dr skew 2970 mb/s, 1485 mb/s ? 28 ? ps 2 270 mb/s ? 37 ? ps 2 s erial output jitter on ddo0 (r c o/ddo1 disabled) t oj 270 mb/s ? 0.02 0.07 ui 3 1485 mb/s ? 0.06 0.10 ui 4 2970 mb/s ? 0.10 0.15 ui 4 s erial output jitter on ddo0 and ddo1 (both ddo0 and ddo1enabled) t oj 270 mb/s ? 0.02 0.07 ui 3 1485 mb/s ? 0.06 0.10 ui 4 2970 mb/s ? 0.11 0.16 ui 4 additive jitter t aj bypass mode, 2970 mb/s ddo0 enabled ?15 ? ps ? bypass mode, 2970 mb/s ddo0 and ddo1 enabled ?20 ? ps ?
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 11 of 27 loop bandwidth bw loop 2.97 g b/s, kbb = v cc ?1.75 ? mhz ? 2.97 g b/s, kbb = float ? 3.5 ? mhz ? 2.97 g b/s, kbb = g nd, <0.1db peaking ?7.0 ? mhz ? 1.485 g b/s, kbb = v cc ?0.875 ? mhz ? 1.485 g b/s, kbb = float ? 1.75 ? mhz ? 1.485 g b/s, kbb = g nd, <0.1db peaking ?3.5 ? mhz ? 270 mb/s, kbb = v cc ?0.16 ? mhz ? 270 mb/s, kbb = float ? 0.32 ? mhz ? 270 mb/s, kbb = g nd, <0.1db peaking ?0.64 ? mhz ? note s : 1. ddo0 to ddo1 skew alignment as defined here: . 2. ddo0 to rco skew alignment as defined here: 3. kbb = float, prn = 2 23 -1, input jitter = 40ps p-p . 4. kbb = float, prn = 2 23 -1, input jitter = 20ps p-p . table 2-2: ac electrical characteristics (continued) v cc = 3.3v 5%, t a = 0 c to 70 c , unless otherwise shown. typical values: v cc = 3.3v and t a =25 c parameter symbol conditions min ty p max units notes ddo0 ddo1 dd s kew ddo0 r c o dr s kew
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 12 of 27 figure 2-1: s erial digital input s ignal s wing figure 2-2: s erial digital output s ignal s wing v s id v s id 2 v s id 2 v s id 2 + 0 v s id 2 _ v s id 2 v cc _ v s id 2 v cc _ v cc v dd s ingle-ended s wing (ddix) s ingle-ended s wing (ddix) differential s wing (ddix-ddix) v od v od 2 v od 2 v od 2 + 0 v od 2 _ v od 2 v cc _ v od 2 v cc _ v cc v dd s ingle-ended s wing (ddo0, ddo1, r c o) s ingle-ended s wing (ddo0,ddo1, r c o) differential s wing (ddo0-ddo0) (ddo1-ddo1) (r c o-r c o)
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 13 of 27 3. input/output circuits figure 3-1: ttl inputs figure 3-2: loop filter figure 3-3: c rystal input v ref lf+ lf- 5k 10p 250r 250r 5k xtal+ xtal-
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 14 of 27 figure 3-4: c rystal output buffer figure 3-5: s erial data outputs, s erial c lock outputs figure 3-6: kbb figure 3-7: indicator outputs: s d/ hd , lo c ked, lo s 1k 1k xtal out- xtal out+ 50 ddo0 / rco/ddo1 ddo0 / rco/ddo1 50 kbb v th2 v th1
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 15 of 27 figure 3-8: s tandard s elect/indication bi-directional pins figure 3-9: s erial data inputs 24k ss[2:0] auto/man 50 ddi[3:0] ddi[3:0] 1k 1k 50 ddi_vtt
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 16 of 27 4. detailed description the GS2975A is a multi-rate se rial digital reclocker design ed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the GS2975A will recover the em bedded clock signal and re-time the data from a smpte 424m, smpte 292m, or smpte 259m -c compliant digital video signal. using the functional block diagram ( page 2 ) as a guide, slew rate phase lock loop (s-pll) on page 16 to on page 21 describes each aspect of the GS2975A in detail. 4.1 slew rate phase lock loop (s-pll) the term ?slew? refers to the output phase of the pll in response to a step change at the input. linear plls have an output phase response characterized by an exponential response whereas an s-pll?s output is a ramp response (see figure 4-1 ). because of this non-linear response characteristic, traditional small signal analysis is not possible with an s-pll. figure 4-1: pll c haracteristics 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui)
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 17 of 27 the s-pll offers several advantages over th e linear pll. the loop bandwidth of an s-pll is independent of the transition density of the input data. pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. the loop bandwidth of a linear pll will change proportionally with this change in transition density. with an s-pll, the loop bandwidth is defined by the jitter at the data input. this translates to infinite loop bandwidth with a zero jitter input signal. this allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. the loop bandwidth of the GS2975A?s pll is defined at 0.2ui of input jitter. the pll consists of two acquisition loops. first is the frequency acquisition (fa) loop. this loop is active when the device is not locked and is used to achieve lock to the supported data rates. second is the phase acquisition (pa) loop. once locked, the pa loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 vco the internal vco of the GS2975A is an lc os cillator. it is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. integrated into the vco is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 charge pump during frequency acquisition, the charge pump has two states, ?pump-up? and ?pump-down,? which is produced by a leading or lagging phase difference between the input and the vco frequency. during phase acquisition, there are two levels of ?pump-up? and two levels of ?pump down? produced for leading and lagging phase difference between the input and vco frequency. this is to allow for greater precision of vco control. the charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, c lf . the instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor.
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 18 of 27 4.4 frequency acquisit ion loop the phase-frequency detector an external crystal of 14.140mhz is used as a reference to keep the vco centered at the last known data rate. this allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. the crystal reference is also used to clock internal timers and counters. to keep the optimal performance of the reclocker over all operatin g conditions, the crystal fr equency must be 14.140mhz, +/-50ppm. the go1535 meets this specific ation and is availa ble from gennum. the go1535 requires an external resistor to be placed in series with the crystal. the optimal value of this resistor can range fr om 100 to 150 ohms, and this value will depend upon the design. for systems which expect to see a higher noise floor, the higher resistor value is recommended. the higher resistor value will work to decrease the loop gain of the oscillator, as well as attenuate noise. the vco is divided by a selected ratio which is dependant on the input data rate. the resultant is then compared to the crystal frequency. if the divided vco frequency and the crystal frequency are within 1% of each ot her, the pll is considered to be locked to the input data rate. 4.5 phase acquisition lo op the phase detector the phase detector is a digital quadrature ph ase detector. it indicates whether the input data is leading or lagging with respect to a clock that is in phase with the vco (i-clk) and a quadrature clock (q-clk). when the phase acquisition loop (pa loop) is locked, the input data transition is aligned to the falling edge of i-clk and the output data is re-timed on the rising edge of i-clk. during high input jitter conditions (>0.25ui), q-clk will sample a different value than i-clk. in this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the vco. figure 4-2: phase detector c haracteristics when the pa loop is active, the crystal frequency and the incoming data rate are compared. if the resultant is more that 2%, the pll is considered to be unlocked and the system jumps to the fa loop. i-phase alignment edge data re-timing edge q -phase alignment edge 0.25ui 0.8ui i- c lk q - c lk input data with j itter re-timed output data
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 19 of 27 4.6 4:1 input mux the 4:1 input mux allows the connection of four independent streams of video/data. there are four differential inputs (ddi[3:0] and ddi[3:0] ). the active channel can be selected via the ddi_sel[1:0] pins. table 4-1 shows the input selected for a given state at ddi_sel[1:0]. the ddi inputs are designed to be dc inte rfaced with the output of the gs2974 cable equalizer. there are on-chip 50 termination resistors which come to a common point at the ddi_vt pins. connect a 10nf capacitor to this pin and connect the other end of the capacitor to ground. this terminates the transmission line at the inputs for optimum performance. if only one input pair is used, connect the unused positive inputs to +3.3v and leave the unused negative inputs floating. this helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 automatic and manual data rate selection the GS2975A can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. the auto/man pin selects automatic data rate detection mode (auto mode) when high and manual data rate selection mode (manual mode) when low. in auto mode, the ss[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the pll is locked to (or previously locked to). the ?search algorithm? cycles through the data rates and starts over if that data rate is not found (see figure 4-3 ). figure 4-3: data rate s earch pattern table 4-1: bit pattern for input select ddi_sel[1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3 270m b /s 2.970(2. 6 97)g b /s 1.485(1.4835)g b /s
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 20 of 27 in manual mode, the data rate can be prog rammed and the ss[2:0] pins become inputs. in this mode, the search algorithm is disabled and the pll will only lock to the data rate selected. table 4-2 shows the ss[2:0] pin settings for either the data rate selected (in manual mode) or the data rate that the pll has locked to (in auto mode). 4.8 bypass mode in bypass mode, the GS2975A passes the data at the inputs directly to the outputs. there are two pins that control the bypass function: bypass and autobypass. when bypass is set high, the gs 2975a will be in bypass mode. when autobypass is set high, the GS2975A will be configured to enter bypass mode only when the pll has not locked to a data rate. when bypass is set high, autobypass will be ignored. when the pll is not locked, and both bypa ss and autobypass are set low, the serial digital output ddo0/ddo0 or ddo1/ddo1 will produce invalid data. 4.9 dvb-asi operation the GS2975A will also re-clock dvb-asi at 270 mb/s. in auto mode, the device will automatically lock to the incoming 270mb/s signal. in manual mode, the ss[2:0] pins must be set to 010 (270 mb/s) to ensure prop er operation. 4.10 lock and los the locked signal is an active high outp ut which indicates when the pll is locked. the internal lock logic of the GS2975A incl udes a system which monitors the frequency acquisition loop and the phase acquisition loop as well as a monitor to detect harmonic lock. the los (loss of signal) output is an active high output which indicates the absence of data transitions at the ddix input. in order for this output to be asserted, transitions must not be present for a period of t la = 5 - 10 s. after this output has been asserted, los will de-assert within t ld = 0 - 5 s after the appearance of a transition at the ddix input. table 4-2: data rate indi cation/selecti on bit pattern ss[2:0] data rate (mb/s) 010 270 101 1485 (1483.5) 110 2970 (2967)
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 21 of 27 figure 4-4: lo s signal timing note: los is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. 4.11 output drivers and output mute the GS2975A offers a choice of dual reclocke d data outputs or one data output and one recovered clock output. table 4-3 shows the correlation of the output pins to the corresponding input select pins. data lo s t la t ld table 4-3: configuration of output drivers and output mute pins ddo_mute rco_mute data/clock ddo0 rco/ddo1 11 0data c lo c k 1 1 1 data data 01 0mute c lo c k 0 1 1 mute mute 10 xdatapower down 0 0 x mute power down note: mute = outputs latched at previous data bit. power down = outputs pulled to v cc through 50 resistor.
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 22 of 27 5. typical application circuit figure 5-1: gs 2975a typical application c ircuit note: the GS2975A is drop-in co mpatible with the gs2975 application circuit. in the gs2975 application circuit pin 37 is connected to ground. if the GS2975A is dropped into the gs2975 application circuit, the rco/ddo1 and rco/ddo1 pins will output the recovered clock. ddi_sel1 ddo_mute ddi_sel0 locked sd/hd 3.3v 3.3v 3.3v 3.3v 10n 10n 10n 10n 47n GS2975A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 4 6 47 48 49 50 51 52 53 54 55 5 6 57 58 59 6 0 6 1 6 2 6 3 6 4 ddi0 ddi0_vt ddi0 gnd ddi1 ddi1_vt ddi1 gnd ddi2 ddi2_vt ddi2 gnd ddi3 ddi3_vt ddi3 gnd ddi_sel0 ddi_sel1 bypass autobypass auto/man vcc_vco vee_vc0 ss0 ss1 ss2 nc locked los vcc_dig vee_dig gnd sd/hd kbb ddo_mute rco_mute rsv rco/ddo1 vcc_rco vee_rco gnd ddo0 rsv ddo0 vcc_ddo vee_ddo gnd xtal_out+ xtal_out- xtal+ xtal- nc vee_cp vcc_cp lf- lf+ nc 10n (14.140mhz) 10n 10n 10n data input 1 data input 0 data input 3 data input 2 data output zo = 50 zo = 50 zo = 50 zo = 50 zo = 50 3.3v 10n 100 go1535 note: all resistors in ohms an d all c apa c itors in fara d s. nc nc nc nc nc rco/ddo1 clock output zo = 50 los rco_mute data/clock data/clock
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 23 of 27 6. package & ordering information 6.1 package dimensions a b 9.00 4.50 4.50 9.00 2x 2x 0.15 c 0.15 c 0.10 c 0.08 c 64x s eatin g plane 0.90 +/- 0.10 +0.03 0.02-0.02 0.20 ref c 7.10+/-0.15 3.55 0.40+/-0.05 7.10+/-0.15 3.55 0.25+/-0.05 64x 0.10 c ab c 0.05 0.50 all dimen s ion s in mm pin 1 area c entre tab 45 45 0.3+/-0.05
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 24 of 27 6.2 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensions shou ld conform to customer design rules and process optimization. note: all dimensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 c enter pad
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 25 of 27 6.3 packaging data 6.4 marking diagram parameter value package type 9mm x 9mm 64-pin qfn moisture s ensitivity level (per jede c j- s td-020 c )3 junction to c ase thermal resistance, j-c 9.1 c /w junction to air thermal resistance, j-a (at zero airflow) 21.5 c /w junction to board thermal resistance, j-b 5.6 c /w psi, 0.2 c /w pb-free and roh s c ompliant yes GS2975A xxxxe3 yyww pin 1 id xxxxe3 yyww yyww - date c ode yy - 2-digit year ww - 2-digit week number xxxx - l ot/work order id
GS2975A hd-linx? iii multi-rate sdi automatic reclocker with dual differential outputs data sheet 41487 - 4 april 2009 26 of 27 6.5 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 6-1 . the recommended standard pb reflow profile is shown in figure 6-2 . figure 6-1: maximum pb-free s older reflow profile (preferred) figure 6-2: s tandard pb s older reflow profile 6.6 ordering information 25c 150c 200c 217c 2 6 0c 250c time temperature 8 min. max 6 0-180 se c . max 6 0-150 se c . 20-40 se c . 3c/se c max 6 c/se c max 25c 100c 150c 183c 230c 220c time temperature 6 min. max 120 se c . max 6 0-150 se c . 10-20 se c . 3c/se c max 6 c/se c max part number package temperature range gs 2975a gs 2975a c ne3 pb-free 64-pin qfn 0 c to 70 c gs 2975a gs 2975a c nte3z pb-free 64-pin qfn 2,500pc reel 0 c to 70 c
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